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SPI-BUS, Kraftfahrzeuge, 4 kbit (512x8 Bit), EEPROM - BR25H040FVM-2CBR25H040-2C ist ein serieller EEPROM der SPI-BUS-Schnittstellenmethode.
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Spezifikationen:
| Grade | Automotive |
| I/F | SPI BUS |
| Density [bit] | 4K |
| Bit Format [Word x Bit] | 512 x 8 |
| Package | MSOP8 |
| Operating Temperature (Min.)[°C] | -40 |
| Operating Temperature (Max.)[°C] | 125 |
| Vcc(Min.)[V] | 2.5 |
| Vcc(Max.)[V] | 5.5 |
| Circuit Current (Max.)[mA] | 4.0 |
| Standby Current (Max.)[μA] | 10.0 |
| Write Cycle (Max.)[ms] | 4.0 |
| Input Frequency (Max.)[Hz] | 10M |
| Endurance (Max.)[Cycle] | 106 |
| Data Retention (Max.)[Year] | 40 |
Eigenschaften:
- ・ High speed clock action up to 10MHz (Max.)
・ Wait function by HOLDB terminal.
・ Part or whole of memory arrays settable as read only memory area by program.
・ 2.5V to 5.5V single power source action most suitable for battery use.
・ Page write mode useful for initial value write at factory shipment.
・ For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
・ Self-timed programming cycle.
・ Low Supply Current At write operation (5V) : 1.0mA (Typ.) At read operation (5V) : 1.0mA (Typ.) At standby operation (5V) : 0.1μA (Typ.)
・ Address auto increment function at read operation
・ Prevention of write mistake Write prohibition at power on. Write prohibition by command code (WRDI). Write prohibition by WPB pin. Write prohibition block setting by status registers (BP1, BP0). Prevention of write mistake at low voltage.
・ MSOP8, TSSOP-B8, SOP8, SOP-J8 Package
・ Data at shipment Memory array: FFh, status register BP1, BP0 : 0
・ More than 100 years data retention.
・ More than 1 million write cycles.
・ AEC-Q100 Qualified.
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