In CMOS output type reset ICs, the output MOS transistor at the power supply side is Pch MOS, and at the ground side it's Nch MOS, meaning that the 'L' output voltage utilizes Nch operation and the 'H' output voltage Pch.
There is no diode between the input and output. Discharging the output capacitor is performed by turning ON the output transistor when the reset output becomes 'L' due to power supply drop. IOL listed in the datasheet becomes the discharge current capacity.
This is the voltage range supplied to the normally operating VDD pin. The reset 'L' output may not be retained if it falls below the minimum specified value (maximum specified value for the BD47x series of bipolar reset ICs).
Unless otherwise specified, the maximum value of the operating voltage range VOPL is the absolute maximum rated supply voltage. Be careful not to exceed the absolute max. ratings, even instantaneously.
In the case of open-drain output, the detection voltage drops and when VDD falls below the operating voltage limit (VOPL) from the state where the output of the reset IC is 'L', the voltage at the pull-up location of the output resistor is output in order to turn OFF the output NMOS transistor. Also, in the case of CMOS output, when VDD drops below VOPL at 'L' output the NMOS transistor turns OFF and the output voltage is near VDD. In addition, when VDD drops below the threshold value of the PMOS transistor the output goes to high impedance and becomes undefined. In both cases (open-drain and CMOS outputs), when VDD is in the range from 0V to VOPL the output is hung at VDD and is raised, but in the event a slight rise will cause system problems we recommend connecting a capacitor at the output. Since the above operation will vary depending on the application, confirm under actual conditions.
The BU42xx/43xx and BU48xx/49xx series features a through-current of several mA, so we do not recommend using a resistor divider. For other models, the through-current is on the order of tens to hundreds of uA.