Häufig gestellte Fragen (FAQ) |ROHM Semiconductor

What does Nch and Pch mean in the column for 'L' and 'H' output voltages listed in the datasheet for reset ICs?
- In CMOS output type reset ICs, the output MOS transistor at the power supply side is Pch MOS, and at the ground side it's Nch MOS, meaning that the 'L' output voltage utilizes Nch operation and the 'H' output voltage Pch.

How do you handle the NC pins for reset ICs?
- Since the NC pins are isolated from the chip, there is no problem connecting them to VDD, ground, or open.

What is the maximum permissible output current for reset ICs?
- The datasheet lists the absolute maximum rated output current. At the same time, please ensure that the product of output voltage and output current is below the permissible loss.

For reset ICs, is there a built-in diode that discharges the remaining charge in the external capacitor when the power supply is OFF?
- There is no diode between the input and output. Discharging the output capacitor is performed by turning ON the output transistor when the reset output becomes 'L' due to power supply drop. I_OL listed in the datasheet becomes the discharge current capacity.

For reset ICs, is the operating voltage range specification V_OPL the operating voltage range of the VDD pin?
- This is the voltage range supplied to the normally operating VDD pin. The reset 'L' output may not be retained if it falls below the minimum specified value (maximum specified value for the BD47x series of bipolar reset ICs).

For reset ICs, will the output remain at 'L' even if the supply voltage VDD falls below the operating voltage limit (V_OPL)?
- In the case of open-drain output, the detection voltage drops and when VDD falls below the operating voltage limit (V_OPL) from the state where the output of the reset IC is 'L', the voltage at the pull-up location of the output resistor is output in order to turn OFF the output NMOS transistor. Also, in the case of CMOS output, when VDD drops below V_OPL at 'L' output the NMOS transistor turns OFF and the output voltage is near VDD. In addition, when VDD drops below the threshold value of the PMOS transistor the output goes to high impedance and becomes undefined. In both cases (open-drain and CMOS outputs), when VDD is in the range from 0V to V_OPL the output is hung at VDD and is raised, but in the event a slight rise will cause system problems we recommend connecting a capacitor at the output. Since the above operation will vary depending on the application, confirm under actual conditions.

What is the through-current for each model of reset IC?
- The BU42xx/43xx and BU48xx/49xx series features a through-current of several mA, so we do not recommend using a resistor divider. For other models, the through-current is on the order of tens to hundreds of uA.

Will reset ICs operate even if the power supply rise time is delayed?
- Since reset ICs monitor the DC voltage, they operate even if the power supply VDD rise time is delayed.