For reset ICs, what is the recommended capacitance range for the capacitor connected to the CT pin for variable delay time (flexible delay time setting) products and the expected problems that may occur if setting outside the recommended range?
The recommended capacitance range at the CT pin is 100pF to 0.1uF (open to 4.7uF for the BD52xx-2C/BD53xx-2C series). Also take into consideration the parasitic capacitance and confirm operation accordingly. If the CT capacitance is small when the VDD rise is fast the output may become 'H' without outputting 'L' first. Therefore, insert a capacitor between VDD and ground to delay the rise. If the CT capacitance is large the slope of the CT charging waveform will decrease, which may cause chattering at the output due to noise, but this can be reduced by inserting a 1000pF capacitor between the output and ground.