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In the datasheet for fixed delay time (built-in counter timer) type reset ICs why is an external resistance of 100kΩ recommended between the VDD and ER pins as a countermeasure for leakage between ER and ground?
When the external resistance connected to the ER pin is high there is a possibility of current leakage through the substrate between ER and ground and voltage drop due to this external series resistance, so 100kΩ at most is recommended. Therefore, please use as small a resistance as possible.