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For reset ICs, there is a phenomenon where the output voltage rises before the reset voltage goes to 'L' during power supply startup, so explain how to make this as small as possible.
Connecting a capacitor of around 1000pF between output and ground will make it possible to suppress output voltage rise. Regarding output format, since the output of CMOS output features a voltage lower than the operating supply voltage vs open drain types, higher resistance is achieved, minimizing output voltage rise during startup.